kw.\*:("Red lógica programable")
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Design of reprogrammable FPLARAJSUMAN, R.Electronics Letters. 1989, Vol 25, Num 11, pp 715-716, issn 0013-5194, 2 p.Article
Function symmetries and decoded-PLA realizationEKTARE, A. B; AL-SHEAKHLY, M. K. H.Computers & electrical engineering. 1988, Vol 14, Num 3-4, pp 137-150, issn 0045-7906Article
A new approach to the design of testable PLA'sREDDY, S. M; DONG SAM HA.IEEE transactions on computers. 1987, Vol 36, Num 2, pp 201-211, issn 0018-9340Article
Reprogrammable FPLA with universal test setRAJSUMAN, R; MALAIYA, Y. K; JAYASUMANA, A. P et al.IEE proceedings. Part E. Computers and digital techniques. 1990, Vol 137, Num 6, pp 437-441, issn 0143-7062Article
Fault equivalence in PLAs and prevention designLIU, B.-D; SHAW, G.-T.Electronics Letters. 1990, Vol 26, Num 23, pp 1925-1926, issn 0013-5194Article
Three-step heuristic algorithm for optimal PLA column foldingYANG, Y.-Y; KYUNG, C.-M.Electronics Letters. 1988, Vol 24, Num 17, pp 1088-1090, issn 0013-5194Article
Built in test of folded PLAsFERNANDES, A. O; COURTOIS, B.Rapport de recherche - IMAG. 1988, issn 0750-7380, 23 p.Report
On the design of a redundant programmable logic array (RPLA)CHIN-LONG WEY; MAN-KUAN VAI; LOMBARDI, F et al.IEEE journal of solid-state circuits. 1987, Vol 22, Num 1, pp 114-117, issn 0018-9200Article
Accelerating run-time reconfiguration on custom computing machinesHERON, J.-P; WOODS, R. F.SPIE proceedings series. 1998, pp 595-607, isbn 0-8194-2916-3Conference Paper
Architecture of field-programmable gate arrays : Field programmable gate arraysROSE, J; ABBAS EL GAMAL; SANGIOVANNI-VINCENTELLI, A et al.Proceedings of the IEEE. 1993, Vol 81, Num 7, pp 1013-1029, issn 0018-9219Article
An algorithm for multiple output minimizationGURUNATH, B; BISWAS, N. N.IEEE transactions on computer-aided design of integrated circuits and systems. 1989, Vol 8, Num 9, pp 1007-1013, issn 0278-0070Article
Characteristics of a programmable logic unitMURAYAMA, T; YAMADA, H; NAKAMURA, T et al.Systems and computers in Japan. 1987, Vol 18, Num 9, pp 31-43, issn 0882-1666Article
Réalisation des algorithmes parallèles de déduction logique dans un milieu matriciel homogèneGORDIENKO, E. K; ZAKHAROV, V. N; MIRONOV, A. YU et al.Izvestiâ Akademii nauk SSSR. Tehničeskaâ kibernetika. 1986, Num 5, pp 153-197, issn 0002-3388Article
A tableaux calculus for ambiguous quantificationMONZ, C; DE RIJKE, M.Lecture notes in computer science. 1998, pp 232-246, issn 0302-9743, isbn 3-540-64406-7Conference Paper
Programmierbare Logik im Test : Bedeutung von Boundary-Scan und ISP für PLD und FPGA = Programmable logic put on the test : The meaning of Boundary-Scan and ISP for PLD and FPGABEACHLER, R. K.F & M. Feinwerktechnik, Mikrotechnik, Messtechnik. 1996, Vol 104, Num 5, pp 346-348, issn 0944-1018Article
Minimum memory buffers in DSP applicationsADE, M; LAUWEREINS, R; PEPERSTRAETE, J. A et al.Electronics Letters. 1994, Vol 30, Num 6, pp 469-471, issn 0013-5194Article
Minimization algorithm for non-concurrent PLAsDUECK, G. W; BUTLER, J. T.International journal of electronics. 1992, Vol 73, Num 6, pp 1113-1119, issn 0020-7217Article
Heuristic algorithm for the minimisation of generalised Beolean functionsCARUSO, G.IEE proceedings. Part E. Computers and digital techniques. 1988, Vol 135, Num 2, pp 108-116, issn 0143-7062Article
A novel technique for efficient parallel implementation of a classical logic/fault simulation problemPRADIP BOSE.IEEE transactions on computers. 1988, Vol 37, Num 12, pp 1569-1577, issn 0018-9340Article
A random-pattern testable design for programmable logic arraysFUJIWARA, H.Systems and computers in Japan. 1987, Vol 18, Num 7, pp 95-102, issn 0882-1666Article
Optical programmable cellular logic array for image processingLIREN LIU; XIAOBEN LIU; BO CUI et al.Applied optics. 1991, Vol 30, Num 8, pp 943-949, issn 0003-6935Article
Efficient algorithm for Weinberger array foldingSAIT, S. M; MUHAMMAD ABDUL-AZIZ AL-RASHED.International journal of electronics. 1990, Vol 69, Num 4, pp 509-518, issn 0020-7217Article
PLA logic minimization by simulated annealingYAO, X; LIU, C. L.Integration (Amsterdam). 1990, Vol 9, Num 3, pp 243-257, issn 0167-9260Article
Testable design of two-dimensional cellular logic arrays for detecting stuck-at and bridging faultsBIDYUT GUPTA; BHATTACHARYA, B. B; BASU, G. C et al.Computers & electrical engineering. 1988, Vol 14, Num 3-4, pp 65-74, issn 0045-7906Article
Realization of computers using programmable logic unitsYAMADA, H; NAKAMURA, T; SHIGEI, Y et al.Systems and computers in Japan. 1987, Vol 18, Num 8, pp 47-56, issn 0882-1666Article